Professor Suresh Sitaraman

Suresh Sitaraman

Professor of Mechanical Engineering
School of Mechanical Engineering
Georgia Institute of Technology
Office: MARC 471T
Phone: 404.894.3405 | Fax: 404.894.9342
E-mail: suresh.sitaraman@me.gatech.edu
Visit Website

 

Mechanical Testing

Dr. Suresh Sitaraman is a Professor in the George W. Woodruff School of Mechanical Engineering, and leads the Flexible Hybrid Electronics Initiative at Georgia Tech and directs the Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab at Georgia Tech.   He is a Thrust Leader/Faculty Member, Reliability/Mechanical Design Research, 3D Systems Packaging Research Center; a Faculty Member, Georgia Tech Manufacturing Institute; a Faculty Member, Interconnect and Packaging Center, an SRC Center of Excellence, Institute for Electronics and Nanotechnology; a Faculty Member, Nanoscience and Nanotechnology, Nanotechnlogy Research Center, Institute for Electronics and Nanotechnology; a Faculty Member, Institute of Materials.

Dr. Suresh Sitaraman’s research is exploring new approaches to develop next-generation microsystems.  In particular, his research focuses on the design, fabrication, characterization, modeling and reliability of micro-scale and nano-scale structures intended for microsystems used in applications such as aerospace, automotive, computing, telecommunicating, medical, etc. 

Dr. Sitaraman’s research is developing physics-based computational models to design flexible as well as rigid microsystems and predict their warped geometry and reliability.  His virtual manufacturing tools are able to simulate sequential fabrication and assembly process mechanics to be able to enhance the overall yield, even before prototypes are built.   Dr. Sitaraman’s work is developing free-standing, compliant interconnect technologies that can mechanically decouple the chip from the substrate without compromising the overall electrical functionality.  This work is producing single-path and multi-path interconnect technologies as well as nanowire and carbon nanotube interconnects for electrical and thermal applications, and such interconnect technologies can be employed in flexible as well as 3D microelectronic systems.  Dr. Sitaraman’s research is also developing innovative material characterization techniques such as the stressed super layer technique as well as magnetic actuation test that can be used to study monotonic and fatigue crack propagation in nano- and micro-scale thin film interfaces.  In addition, Dr. Sitaraman has developed fundamental modeling methodologies combined with leading-edge experimentation techniques to study delamination in the dielectric material and copper interface used in back-end-of-the-line (BEOL) stacks and through-silicon vias as well as epoxy/copper and epoxy/glass interfaces as in microelectronic packaging and photovoltaic module applications.  Examining the long-term operational as well as accelerated thermal cycling reliability of solder interconnects, his work has direct implications in implantable medical devices, photovoltaic modules, computers and smart devices as well as rugged automobile and aerospace applications. 

Through the above-mentioned fundamental and applied research and development pursuits, Dr. Sitaraman’s work aims to address some of the grand challenges associated with clean energy, health care, personal mobility, security, clean environment, food and water, and sustainable infrastructure


Publications

  1. Okereke, R. and Sitaraman, S. K., “Mixed Array of Compliant Interconnects to Balance Mechanical and Electrical Characteristics,” ASME Transactions – Journal of Electronic Packaging, Sep. 2015, Vol. 137, pp. 0310061- 0310069.
  2. Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S., “Study of Chip-Package Interaction Parameters on Interlayer Dielectric Crack Propagation,” IEEE Transactions on Device and Materials Reliability, Vol. 14, No. 1, March 2014, pp. 57-65.
  3. Ginga, N. J., Chen, W., and Sitaraman, S. K., “Waviness reduces effective modulus of carbon nanotube forests by several orders of magnitude,” Carbon, Volume 66, January 2014, pp. 57–66.
  4. Liu, X., Thadesar, P. A., Taylor, C. L., Kunz, M., Tamura, N., Bakir, M. S., and Sitaraman, S. K.,  "Dimension and Liner Dependent Thermomechanical Strain Characterization of Through-Silicon Vias using Synchrotron X-ray Diffraction," Journal of Applied Physics, Vol. 114, p. 064908, 2013.
  5. Ostrowicki, G. T., Fritz, N. T., Okereke, R. I., Kohl, P. A., and Sitaraman, S. K., “Domed and Released Thin Film Construct – An Approach for Material Characterization and Compliant Interconnects,” IEEE Transactions on Device and Materials Reliability,” Vol. 12, No. 1, March 2012, pp. 15-23.
  6. Tunga, K. and Sitaraman, S. K., "Fatigue Life Prediction of Lead-free Solders using Laser Moiré Interferometry," Microelectronics Reliability, Vol. 50, Issue 12, Dec. 2010, pp. 2026-2036.

Patents

  1. Kacker, K., Sokol, T., and Sitaraman, S. K., “Variable Interconnect Geometry for Electronic Packages and Fabrication Methods,” U. S. Patent No. 8,766,449 B2, July 1, 2014.
  2. Kacker, K. and Sitaraman, S. K., “Compliant Off-Chip Interconnects for Use in Electronic Packages and Fabrication Methods,” U. S. Patent No. 8,382,489 B2, Feb. 26, 2013.
  3. Kacker, K. and Sitaraman, S. K., “Compliant Off-Chip Interconnects for use in Electronic Packages,” U. S. Patent No. 8,206,160 B2, June 26, 2012. 
  4. Sitaraman, S. K., Ma, L., and Zhu, Q., “Multi-Axis Compliance Spring,” U.S. Patent No. 7,011,530, March 14, 2006.
  5. Zhu, Q., Ma, L., and Sitaraman, S. K., “Complaint Off-Chip interconnects,” U.S. Patent No. 6,784,378, August 31, 2004.

Selected Awards

  • ASME/EPPD (Electronic and Photonic Packaging Division) – Applied Mechanics Award, 2012
  • Thomas French Achievement Award, Department of Mechanical and Aerospace Engineering, The Ohio State University, 2012
  • Sustained Research Award, Sigma Xi, Georgia Institute of Technology, 2008
  • Outstanding Faculty Leadership Award for the Development of Graduate Research Assistants, Georgia Institute of Technology, 2006
  • 2004 Commendable Paper Award, IEEE Transactions on Advanced Packaging, “The SOP for Miniaturized, Mixed-Signal Computing, Communication, and Consumer Systems of the Next Decade,” May 2004
  • Fellow - ASME International, 2004
  • 2001 Best Paper Award, IEEE Transactions on Components and Packaging Technologies, "Interfacial Fracture Toughness for Delamination Growth Prediction in a Novel Peripheral Array Package," V. Sundararaman and S. K. Sitaraman.
  • 2000 Best Paper Award, IEEE Transactions on Components and Packaging Technologies, "Development of Virtual Reliability Methodology for Area-Array Devices used in Implantable and Automotive Applications," S. K. Sitaraman, R. Raghunathan, and C. E. Hanna
  • Metro-Atlanta Engineer of the Year in Education Award, 1999
  • NSF CAREER Award - 1997-2002

 

Google Scholar Page of this scholar